At the beginning of the HPCC Program in 1991, few computer hardware vendors were developing scalable parallel computing systems, even though they acknowledged that traditional vector computers were approaching their physical limits. By 1993, all major U.S. vendors had adopted scalable parallel technology. Today, a wide range of new computing technologies is being introduced into commercial systems that are now being deployed at the HPCRCs, in industry, and in academia. These include the whole range of scalable parallel and traditional systems such as fine- and coarse-grained parallel architectures, vector and vector/parallel systems, networked workstations with high speed interfaces and switches, and heterogeneous platforms connected by high speed networks. Some of these systems now scale to hundreds of gigaflops (billions of floating point operations per second). The HPCC Program is well on track toward meeting its FY 1996 goal of demonstrating the feasibility of affordable multipurpose systems scalable to teraflops (trillions of floating point operations per second) speeds.
The architectures of scalable systems -- how the processors connect to each other and to memory, and how the memory is configured (shared or distributed) -- vary widely. How these architectures communicate with storage systems such as disks or mass storage and how they network with other systems also differ.
Simulation of the behavior of materials at the fundamental atomic scale (adsorption and diffusion of germanium on a reconstructed Si(100 ) surface). Simulated using the iPSC/860 hypercube and the Paragon XP/S- 5 supercomputers.
In past years, the HPCC Program concentrated on the design and manufacture of high performance systems, including fundamental underlying components, packaging, design tools, simulations, advanced prototype systems, and scalability. ARPA is the primary HPCC agency involved in developing this underlying scalable systems technology, often cost-shared with vendors, for the high performance computing systems placed at HPCC centers across the country. Efforts are still devoted to developing the foundation for the next generation of high performance systems, including new system components that overcome speed and power limitations, scalable techniques to exploit mass storage systems, sophisticated design technology, and ways to evaluate system performance. Additional effort is now being devoted to developing systems software, compilers, and environments to enable a wide range of applications.
Scaling of memory chip technology is essential to increase both speed and capacity of computer-based systems. This figure shows details of 16 memory cells in a high density 1 megabit Static Random Access Memory (SRAM) that were created and visualized using advanced model tools for integrated circuit and technology design developed at Stanford University. Each color represents a physical layer of material (grey-silicon, yellow- silicon oxide, pink-polysilicon, teal-local interconnect and blue-metal) which has been patterned using advanced lithography and etching techniques. The details of geometries and spacings between the various layers are critical in determining both the performance of the SRAM and its manufacturability. Solid geometry models and three-dimensional simulations of both materials interactions and electrical performance are invaluable in optimizing such high density chips.
(Figure Courtesy of Cypress Semiconductor)
The applications now running on the new systems handle substantially more data -- both input and output -- than on traditional systems. Graphical display is critical to analyzing these data quickly and effectively. For example, output from three-dimensional weather models must be displayed and overlaid with real-time data collected from networked instruments at remote observation stations. Hardware to handle this task well, such as workstations for scientific visualization, is part of a high performance computing environment.
Comparison of Josephson Junction technology with gallium arsenide and CMOS (complementary metal oxide semiconductor) technologies showing potential for dramatic improvements in performance with low power.
The HPCC Program develops and evaluates a variety of innovative technologies that have potential for future use beyond the next generation of systems. Included in these are superconductive devices. These devices have demonstrated blinding speed and exceptionally low power consumption at the chip level, but need to be scaled up to more complex components to be useful. If transferable to the system level, these devices would have major impact on computing and communications switching systems. NSA is developing a technology demonstration of a multigigabit per second 128x128 crossbar switch that is potentially expandable to 1000x1000 at very low power. If successful, the technology will be evaluated in a system level computing application.