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Information Technology:
The 21st Century Revolution
High End
Computing -- Research and Development |

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Overview
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Assembling efficiently usable systems from hardware components-such as processors,
memories, input/output devices, and switches-and from software components-such
as languages, compilers, optimizers, schedulers, and memory managers-is
a complex endeavor that must encompass a vast number of interactions to
produce an architecture that, in turn, enables the development of a successful
leading-edge system. These interactions include those among the components
and their arrangement, power and cooling requirements, the hardware and
the applications, and the systems software with both the underlying hardware
and the applications. Projects described in this section illustrate the
enormous range of approaches to high performance computing including workstation
clusters, distributed mass storage, and computational grids.
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Hybrid technology
multithreaded (HTMT)
architecture
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Petaflops-scale computing faces severe challenges of cost, size, power,
complexity, reliability, efficiency, generality, and programmability.
Even with the extraordinary progress of complementary metal oxide semiconductor
(CMOS) technology and massively parallel processor (MPP) architectures-systems
based on conventional technologies that can sustain throughputs beyond
a petaflop--petaflops-scale computing may not be feasible until after
2010.
The hybrid technology multithreaded
(HTMT) interdisciplinary research project-supported by DARPA, NASA, NSA,
and NSF-is attempting to exploit the superior properties of advanced device
technologies to overcome current barriers to success. Such technologies
include rapid single flux quantum (RSFQ) superconductor logic, optical
communications and holographic storage, and processor-in-memory SRAM and
DRAM chips. Superconductor logic is capable of 100 times the speed and
power efficiency of conventional processors, while fiber optical communications
using time division and wave division multiplexing can exceed wire-based
channel bandwidth by a factor of 100 or more. Optical storage density
and power efficiency using holographic photorefractive techniques may
provide an order of magnitude advantage over today's semiconductor memory
at comparable bandwidths. But efficient computation requires effective
resource management in the presence of extremes in latency and parallelism.
The HTMT architecture has been devised to incorporate adaptive latency-tolerant
mechanisms based on multithreaded processors and an innovative memory-based
proactive task management scheme called "percolation."
A design study, simulation, and analysis
indicate that practical petaflops-scale computing based on the HTMT model is
feasible by 2005, followed by rapid advances leading beyond 10 petaflops. In
FY 2000, researchers are compiling a complete report on the sub-elements of
HTMT, including preliminary tests, data, simulations, sizing, produceability,
performance estimates for a full system, cost estimates, and recommendations,
if warranted, for the follow-on work. Beginning in FY 2000, a 15-month program
will verify critical technologies, further simulate architecture to generate
more accurate specification of the proposed hardware, and study the programming
and execution of the proposed system. This effort may lead to the construction
of a prototype machine.
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An overview of the
HTMT memory architecture. |
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Beowulf: High performance computing with workstation clusters and Linux
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In the NASA-funded Beowulf project-which employs clusters of workstations
to achieve high performance computing-every node is responsible for running
its own copy of the operating system kernel, and nodes are generally sovereign
and autonomous at the kernel level. The Beowulf software environment is
implemented as an add-on to commercially available, royalty-free Linux distributions
including all the software needed for a networked workstation. Beowulf has
been migrated to the RedHat Linux distribution that includes programming
environments developed at various sites and development library packages.
To present a more uniform system image to users and applications, researchers
have extended the Linux kernel to allow a loose ensemble of nodes to participate
in a number of global namespaces. These extensions will cause little increase
in kernel size or complexity and, most importantly, will have negligible
impact on individual processor performance.
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Weather forecasting in a mixed distributed shared memory environment
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NOAA has developed a portable message passing interface (MPI)-based version
of its operational weather forecasting codes. To adapt the vector codes
to NOAA's new IBM SP supercomputer, scientists converted the codes to column
structure to optimize cache usage. A single column version of the global
spectral model (GSM) produced by this conversion now uses observational
input to diagnose differences in model physics. NOAA-supported researchers
are exploring the concurrent use of MPI and OpenMP as they seek the most
efficient programming model to use on future generation mixed distributed
shared memory computing systems.
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MVICH-MPI virtual interface architecture
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MVICH is a DOE/National Energy Research Supercomputer Center (NERSC)-funded
project to provide portable high performance communications for cluster
computing. It is an implementation of MPI for the virtual interface architecture
(VIA). VIA is an industry-standard interface for system area networks
(networks for clusters) that provides protected zero-copy user-space inter-process
communication. MVICH provides a high performance MPI available on a wide
range of commodity networks. MVICH is being developed at LBNL and is distributed
with an open source license. It is part of the same project that is developing
M-VIA, an implementation of VIA for Linux. MVICH implements four protocols
to maximize performance over a range of message sizes. Over the next year,
the project plans to add:
- Support for unreliable VIA.
MVICH will handle dropped and out-of-order packets with negligible additional
latency.
- Improved support for asynchronous
communication using multiple threads.
- Thread safety. This requires
a thread-safe VIA implementation as well as additional support for thread
safety in MVICH.
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Distributed-parallel storage system (DPSS)
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Modern scientific computing involves organizing, moving, visualizing, and
analyzing massive amounts of data at multiple sites around the world. The
distributed-parallel storage system (DPSS) provides scalable high performance
distributed parallel architecture and data handling for building high end
storage systems from low-cost commodity hardware components. It was developed
in the DARPA-funded Multidimensional Applications and Gigabit Internetwork
Consortium (MAGIC) testbed, with additional support from DOE. The DPSS architecture
is a network striped disk array that lets applications determine optimal
data layout, replication and/or code redundancy, security policy, and dynamic
reconfiguration. This technology provides an economical, widely distributed
architecture for caching large amounts of data that can potentially be used
by many different users. Current performance results are 980 Mbps across
a local area network (LAN) and 570 Mbps across a wide area network (WAN).
DPSS is used in Terravision, the terrain navigation application for which
it was designed; in an image viewing application from the U.S. Geological
Survey's (USGS's) Earth Resources Observation Systems (EROS) data center;
and in high-energy physics and medical imaging applications.
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Globus
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We do not think twice about accessing Web pages that are spread across
the globe. The goal of Globus R&D is to bring about a similar revolution
in computation. Globus-a joint project of DOE's Argonne National Laboratory
(ANL) and the University of Southern California's (USC's) Information
Sciences Institute funded by DARPA, DOE, and NSF-is developing the fundamental
technologies to build computational grids, execution environments that
enable an application to integrate geographically distributed instruments,
displays, and computational and information resources. Such computations
may link tens or hundreds of these resources.
Globus focuses on:
- Research into basic problems
in resource management, security, fault tolerance, and algorithms
- Tools, such as prototype software
that can run on a range of platforms
- Large-scale testbeds
- Large-scale grid-enabled applications,
developed in collaboration with application scientists
Participants in the Globus Ubiquitous Supercomputing Testbed Organization (GUSTO)
are testing Globus concepts on a global scale. GUSTO currently spans more than
40 institutions worldwide and includes some of the largest computers in the
world. ANL and USC researchers have won the Global Information Infrastructure
Next Generation Award for their development of GUSTO's Globus-based prototype
for future computational grids. The GII awards recognize and promote best practices
and new models in Internet and network technologies. The Next Generation category
targets exemplary uses of the information infrastructure that demonstrate its
direction and future potential for cutting-edge information and communications
technology applications.
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This image was generated by Synthetic
Forces Express, a large-scale simulation developed at the California Institute
of Technology (CalTech) that uses Globus to provide access to multiple supercomputer
resources. SF Express conducted a record-breaking 100,298-vehicle simulation-the
largest distributed, interactive battlefield simulation to date--executing
it on 1,386 processors distributed over 13 computers at nine sites spanning
seven time zones. |
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Globus: Smart instruments application
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The Synthetic Forces Express (SF Express) project is investigating the use
of high performance computing systems to support very large-scale distributed
interactive simulations. SF Express conducted a record-breaking 100,298-vehicle
simulation-the largest distributed, interactive battlefield simulation to
date-- executing it on 1,386 processors distributed over 13 computers at
nine sites spanning seven time zones. Issues addressed to make this simulation
possible included scalable communications, scenario distribution, resource
configuration, resource management, information logging, monitoring, and
fault tolerance. Global and local services were decoupled, allowing the
application to run in a flexible, resource-aware environment. SF Express
is incorporating emerging computational grid tools and techniques into the
distributed interactive simulation environment to bring pervasive and dependable
access to high end computation.
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Legion: A worldwide virtual computer
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Legion-an object-based metasystem software project at the University of
Virginia funded by the Department of Defense/Naval Oceanographic Office
(DoD/NAVO), NSF, and DOE-will build a system of millions of hosts and
trillions of objects tied together with high-speed links. The interface
will allow users working at home to access data and physical resources-such
as cameras, digital libraries, linear accelerators, physical simulations,
and video streams-as if these resources resided on their own disk drives.
Groups of users will construct shared virtual workspaces to exchange information
and collaborate on research. Legion supports this with transparent scheduling,
data management, fault tolerance, site autonomy, and security options,
achieving high performance by allowing resource selection among available
machines and parallel use of many resources. Legion can be used for parallel
processing in a variety of applications and can execute a single application
across geographically separate hosts or support meta-applications. Legion
supports popular parallel libraries such as MPI and PVM; parallel languages
such as MPL; wrapped parallel components so that legacy and new software
can be aggregated into Legion objects; and exporting the runtime library
interface to library, toolkit, and compiler writers. Legion is an open
system whose runtime library is available and for which third-party development
is encouraged.
Current and planned experimental
applications of Legion include Chemistry at Harvard Molecular Mechanics
(CHARMM) for molecular dynamics and mechanics such as protein-folding
problems; direct simulation-Monte Carlo (DSMC), used at the University
of Virginia to study vapor deposition onto surfaces; and coupled applications
such as a federated climate model that ties together many lower-level
models.
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Java numerics
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The rapid, widespread adoption of the Java language and environment for
network-based computing has created a demand for reliable and reusable numerical
software components to support scientific applications now under development.
NIST is working with the Java Grande Forum (JGF) to assess the use of Java
in high performance computing. The JGF is developing proposals for changing
the language and its environment to overcome identified deficiencies and
coordinate the development of standard applications program interfaces (APIs)
for numerical computing. Several modifications to Java floating point semantics
requested by the JGF Numerics Working Group were made this year, leading
to performance improvements on common microprocessors, and progress is being
tracked with SciMark, a new Web-based benchmark for numerical computations.
A growing collection of proposed APIs for numerical computing in Java is
available at: http://math.nist.gov/javanumerics/.
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Research in advanced hardware components:
Going where ordinary
electronics cannot
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Hardware components, such as microscopic transistors and wires, are the
base of today's computing systems. They make up the processors, memories,
switches, and linkages from which systems are built. The recent astonishing
cost-performance progress in commodity computing systems is based primarily
on progress at the hardware component level. At the high end, architectural
advances are critical, but real breakthroughs are needed at the component
technology level. The HTMT project (page 23) is investigating the use of
RSFQ superconducting devices and holographic memories. The following projects
illustrate how Federally funded basic research can go beyond current semiconductor-based
approaches by using photonics, nuclear magnetic resonance, quantum mechanics,
superconducting electronics, and biomolecules.
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DARPA's very large-scale integration (VLSI) photonics program
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It is not unusual today for commodity processor chips to perform simple
arithmetic operations at speeds ranging from 300 to 600 MHz. These large
computational bandwidths, however, are not yet matched by commensurate
communication bandwidths between the chips. In fact, the wire interconnections
between chips typically operate at only a fraction of the internal computational
bandwidth. Optics has the potential to solve the bandwidth interconnect
problem between chips, between multichip modules, and at the backplane
of boards.
Next generation advanced information
processing systems, such as those expected to be used in real-time synthetic
aperture radar (SAR) imaging, automatic target recognition, and intensive
medical image processing, will require large aggregate computational and
communication bandwidths. Since most of these systems are assembled from
multiprocessor, memory, and special-purpose digital signal processing
chips, the ideal communication bandwidths between them should be on the
order of a terabit per second (Tbps). But Tbps bandwidths cannot, at this
time, be achieved using conventional wire interconnections. The primary
goals of DARPA's VLSI photonics program are to develop and demonstrate
the basic technologies that will bring the benefits of optics to chip-scale
interconnections.
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Quantum computing |
Theoretical computer science in the 1980s and 1990s has conjectured that
a "quantum computer" can solve certain problems asymptotically more rapidly
than conventional computers. Such a quantum computer can be thought of
as an array of complex two-state systems--for example, the atomic nuclei
in molecules with a spin quantum number of 1/2 as is found in hydrogen
protons, each of which can store one quantum bit, or qubit, of information.
NSA is conducting research into quantum computing using quanta of light
as computing elements to demonstrate 1-qubit operations, perform experiments
to achieve 2-qubit operations using the optical-lattice method of trapping
atoms, and simulate the dynamics of a set of qubits in finer detail than
previously achieved. Other NSA-supported projects include experimental
research on quantum dots and Josephson junctions as possible qubits and
an investigation of individual nuclear spins implanted in a silicon crystal
as qubits.
In FY 2000, a consortium of university
and Government laboratories is working on a scalable silicon-based nuclear
spin quantum computer concept. Other research is under way on the characterization
of spin coherence and Rabi oscillations in quantum nanostructures and
on the measurement of decoherence times in superconducting qubits.
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| Quantum phase data
storage and retrieval |
NSF-funded researchers
at the University of Michigan are exploring the possibility that atomic
quantum phases can be used as a database. Data are assigned to a quantum
state in a cesium atom, and a laser burst stores data in the assigned state
by inverting the quantum phase. A second laser burst locates the stored
data by amplifying the inverted state while suppressing the other states.
Although speculative and long-term, this project illustrates the potential
application of experimental physics to information technology.
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Quantum information and computation |
The goal of this DARPA-funded project at the California Institute of Technology
(CalTech), the Massachusetts Institute of Technology (MIT), and USC is
to build and operate devices that can store and process information in
the quantum states of matter. The objectives are to:
- Develop and explore new ideas
for implementing quantum gates in the laboratory
- Broaden the range of problems
known to be efficiently solvable using quantum computing
- Design efficient networks of
quantum gates to solve computationally difficult problems
- Improve the reliability of a
quantum computer that operates under realistic conditions
- Develop a sequential simulator
to validate and optimize models and circuits for quantum computers
- Fabricate devices and conduct
experimental studies of their performance
- Develop quantum networks for
distributed quantum computation and communication
- Explore the applicability of
well-tested many-body methods to quantum computation
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Ensemble quantum computer (EQC) nuclear magnetic resonance (NMR)
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NMR spectroscopy is enabling the ensemble quantum computer, a new computational
model that can, in principle, trade exponential growth in computation time
for exponential increases in the system size needed for quantum computing,
with the price being ensemble averages of microscopic observations. This
DARPA-funded project focuses on several questions:
- How can the algorithms proposed
for quantum computers be implemented efficiently using NMR?
- How can the errors due to imperfect
instrumentation and decoherence be prevented, detected, and/or corrected?
- What computational models other
than EQC can NMR implement?
- What macroscopic spin orders
can be used to practically and efficiently encode information?
- What couplings and feedback
among these orders can be most conveniently implemented?
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DNA data storage |
One gram of DNA contains 1021 DNA
bases, which is equal to 108 terabytes of information storage. A DARPA- and
NSF-funded project at a consortium of nine organizations led by Duke University
is leveraging recombinant DNA techniques-appropriately modified to ensure error
resiliency-to solve NP search problems. (NP problems grow exponentially harder
as the number of items searched increases and becomes intractable using normal
computing.) The key tasks are experimental demonstrations, nanoconstruction
of new 3-D structures, applications, and mathematical models and software tools
for simulation. The basic approach to NP search problems is to perform recombinant
DNA operations to construct a vast number of possible solutions to the input
problem and then perform further recombinant DNA operations to determine which
of these correctly solve the problem.
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A key goal of DNA nanotechnology
is construction of periodic arrays in 2 and 3 dimensions. The project has
produced 2-D arrays from antiparallel double crossover molecules. The first
arrays were produced by using two different double crossover molecules
(top). At the top of this drawing are two double crossover molecules, A
and B*, which are shown schematically. The complementarity between their
sticky ends is represented as geometric complementarity. The * indicates
that the B molecules contain DNA hairpins that project out of the plane
of the helices; these hairpins act as topographic markers in atomic force
microscopy (AFM) (left). The two molecules are approximately 4 nanometers
wide, 16 nanometers long, and 2 nanometers thick. When these two tiles
are mixed in solution, they form hydrogen-bonded 2-D arrays that are several
microns long and hundreds of nanometers wide. The rows of projecting hairpins
appear as stripes when visualized by AFM. The stripes are separated by
about 32 nanometers, as expected. Thus, scientists can create specific
structural features on the nanometer scale by self-assembly techniques.
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Avanced microscpy tools for integrated circuit development
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In order to develop and analyze the performance of the next and future generations
of integrated circuits, NSA's microscopy program will develop knowledge,
techniques, and instruments to fabricate, analyze, and manipulate the morphology
of semiconductor surfaces and structures. The newly developed capabilities
of in-situ direct imaging of surfaces (low energy electron microscopy [LEEM]
and photo emission electron microscopy [PEEM]) with both spatial and temporal
resolution will allow the intrinsic properties of surfaces to be used to
design and characterize atomic-scale structures. Atomic force microscopy
and nearfield scanning probe techniques will provide capabilities for manipulating,
measuring, and confirming desired surface structures. Such capabilities
will provide tools for creating solid state quantum computer test structures.
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3-D diamond multichip module (MCM) cube computer |
A 3-D computer architecture with a nanosecond system clock was completed
in FY 2000 using test equipment developed by NSA and DARPA. After demonstrating
a three-dimensionally interconnected stack of diamond aerosol spray-cooled
MCMs, the subnanosecond clock performance of five-stack 3-D interconnected
diamond substrates verified the modeled performance for delay times through
a "worst case nodal path." The emulated performance of a 40-layer stack
was achieved through the use of "turn-around" boards at the top and bottom
of the five-layer stack. The five-layer stack dissipated 2.5 kilowatts of
heat while the maximum measured temperature on the 16 sensors per layer
was 80 degrees centigrade in the center of the third MCM layer. The 500
watts per MCM were extracted by aerosol spray cooling of the exposed edges
on two sides of the four-sided diamond substrate MCMs. Although this design
used an older "fuzz button" interconnect technology for connecting the stacked
thin-film-layered diamond substrates together (6,200 connections for each
side of the MCM), no observed failures were recorded during the six-week
qualifying tests. These results verified the 3-D concept for a diamond-substrate-based,
aerosol spray-cooled supercomputer design.
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Optical tape |
Existing Government mass data storage capabilities are inadequate to meet
near-term needs, and data rates fall short of what is needed to support
advanced computing. NSA is funding research to develop a higher-capacity
medium compatible with existing systems to save millions of dollars that
would otherwise be spent to expand floor space to house additional mass
storage. Optical tape promises to combine high capacity with high data transfer
rate in removable media. A 25 MBps prototype optical tape drive has been
designed, fabricated, and tested, demonstrating that a user data capacity
of one terabyte could be stored on a 3480-style cartridge. Funding partners
for this project include NSA, NASA, and DOE. A planned follow-on effort
is to modify the LOTS commercial tape drive to achieve data transfer rates
of between 100 and 160 MBps in a single drive and to multiplex to provide
a 320 MBps rate.
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electronics |
The NSA program in
superconducting electronics focuses on high performance computing alternatives
to current silicon and gallium arsenide technologies, which have speed and
power limitations. Prior research suggests that superconducting supercomputers
can deliver very high performance with very low power requirements. For example,
the HTMT project reported above incorporates the use of superconducting electronics.
NSA is funding research to develop a superconductive crossbar switch, a 128
x 128 crossbar switch operating at 2.5 Gbps per port for use in supercomputing
and networking applications. While the crossbar electronics operate at a temperature
of 4 Kelvin and the cryogenic elements are cooled by a refrigerator, the input
and output ports of the switch are at room temperature, providing the user
with normal room-temperature support. Extended to higher speed and size, this
switch is a candidate for use in HTMT. Layout of a 24-chip multichip module
is 95 percent complete. Construction and assembly of the 128 x 128 crossbar
will begin in FY 2001. The chips will be built and the electronics and housing
of the MCM and cables will be completed.
NSA is pursuing sub-nanosecond memory. In order to take advantage of multigigahertz
clock rate processors, multigigahertz memories must be locally available to
the processors. This R&D will demonstrate sub-nanosecond access time superconductor
and semiconductor memory technology and characterize its performance. The technology
is applicable to both HTMT and to the superconductive crossbar switch when
used as a room temperature switching system. So far, circuits have been designed
and verified for the silicon-on- insulator (SOI) implementation, and calculations
and simulations show its feasibility. Chips using sub-micron feature size are
being built for testing. In FY 2001, the SOI version will be tested and characterized
for speed and power, and the superconductive memory will be built and tested.
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Top and side views of a compact
planar surface mount or clampdown package for a 200-ampere NMOS ultra-low
Ron switching FET for low-voltage power converters. Using aerosol spray
cooling to thermally manage the operation of a low-voltage, high-current
power converter enables a radically new design for a silicon NMOS switching
chip capable of operating at relatively high switching rates (>2MHz) while
switching up to 200 amperes of current. The ultra-low resistance of the
device allows power conversion efficiencies to reach as high as 90 percent-a
remarkable value for such low-voltage converters. This inexpensive chip
will play a critical role in high performance computation as bias voltages
are reduced to meet the shrinking photolithographic demands of future machines
that operate with concomitantly higher operating amperage.
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Smart memories |
In FY 2000, NSA-supported smart
memory R&D focused on the basic architecture of a computation tile--a
building block that must efficiently execute applications exhibiting different
types of parallelism. To guide the development, researchers examined how
well the machine could emulate existing machine architectures developed
for different application spaces.The machines chosen for emulation are
the Stanford FLASH, Imagine, hydra, and M-machine.The researchers also
investigated architectures for on-chip internconnetion networks, envisioning
that future VLSI chips will be constructed with a common interconnection
network independent of the function of the chip. The research aims at
discovering new interconnection network architectures that best exploit
the properties of these emerging on-chip networks.
FY 2000 plans include the design
and fabrication of a reconfigurable wiring test chip, the development
of programming models for smart memories, and completion of a proposed
smart memory architecture.
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Vendor partnerships |
Vendor partnerships, which support the continuing development of supercomputing
systems in the U.S., will benefit NSA and are also anticipated to be commercially
successful. In October 1999, SGI/Cray demonstrated a boot of the operating
system on the simulator of the SV2, a scalable hybrid scalar/vector system.
The first node of the SV2 will be fabricated in early FY 2001. The first
64-processor system is expected in late FY 2001 or early FY 2002. NSA also
has partnership agreements with Compaq/Digital Equipment Corporation (DEC)
and Sun Microsystems, Inc., to improve scalar/integer calculations, reduce
memory latency, and increase ease of use. Both vendors are incorporating
NSA's UPC compiler in their commercial systems. DOE and the National Reconnaissance
Office (NRO) participate in requirements specifications and reviews.
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Molecular electronics |
The goal of the DARPA program in "moletronics" is to demonstrate the integration
of multiple molecules and/or nanoparticles into scalable, functional electronic
devices that are interconnected as well as connected to the outside world
in a realistic and practical manner. The aim is to provide moderate computational
power and high-density memory in an extremely small, low-power format, which
will not require multibillion-dollar fabrication facilities. Molecular electronics
will use molecules and/or nanoparticles to achieve further miniaturization,
greater functionality, and faster clock rates for advanced electronic systems
that operate under a wide range of temperatures and preferably take advantage
of 3-D architectures.
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Nanocrystal devices |
The aim of this NSF project
is to develop and demonstrate nanocrystal (NC) and nanocrystal array (NCA)-based
devices by first developing techniques for synthesizing NC-based thin films
for device applications and understanding and optimizing their interfaces
to other materials. Potential applications range from phosphors to photovoltaics
to electronic switching and storage devices. Chemical techniques for fabricating
NC-integrated systems and examining their structures will be developed.
Their optical properties will be studied. Temperature- dependent electron
transport, photovoltaic, and capacitance through NC and NCA systems will
be measured using electron-beam lithography. Interfaces will be characterized
and controlled. This multidisciplinary scientific and engineering research
will contribute basic understanding of key aspects of potentially highly
useful materials and devices and will integrate research and education through
student training.
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New Starts
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New initiative
Measurement and calibration for the virtual sciences
The ongoing revolution in computing,
communications, and information technologies can transform the foundation
for industrial development from physical testing, prototypes, and pilot
plants to a new paradigm based on modeling and simulation, where every
material or process is conceived, designed, characterized, and optimized
using advanced computation and information technology. Yet the methods
and tools that allow users to validate, test, and calibrate models of
designed materials, complex physical processes, and product performance
are missing. Without them, industrial use of these advanced technologies
will lag behind technology development.
Starting in FY 2001, NIST will
begin a program that will include:
- Development and optimization
of broadly applicable methods, algorithms, and associated data to accelerate
industrial use of 21st century computing and information technologies
for modeling and simulating complex materials and processes
- Development of methods and tools
to support the validation, benchmarking, and comparison of models, algorithms,
and software used for modeling and simulating materials and processes,
including carefully constructed and analyzed open reference implementations,
well-characterized test calculations and data, metrics and related tools
for evaluating computed results, and testbeds for particular application
domains
- Development of consensus standards,
definitions, and tools for modeling and simulating information management,
software integration, and software interoperability to enhance modeling
and simulation in an application environment
- Development of user interfaces
for advanced modeling and simulation software and integration with associated
data and information resources from diverse sources including Web-based
databases and archives
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