National Security Agency (NSA)

The goal of NSA's HPCC Program is to accelerate the development and application of the highest performance computing and communications technologies to meet national security requirements and to contribute to collective progress in the Federal HPCC Program.

In support of this goal, NSA:

NSA participates in all five components of the HPCC Program as follows.

HPCS: Heterogeneous High Performance Computing; Balanced Architectures

NSA deploys experimental scalable computer capabilities, emphasizing interoperability of massively parallel machines in a highly heterogeneous environment of workstations, vector supercomputers, and mass storage devices. NSA's HPCS program also emphasizes an open systems approach to development and maintenance of the HPCC environment and the integration of specialized high speed hardware within this environment.

By integrating processing directly into otherwise standard memory chips fabricated at its Special Processing Laboratory, the Supercomputing Research center has developed the Terasys workstation, which outperforms one Cray Y-MP processor by 5 to 48 times on a set of nine NSA applications. A mature software environment, available for the workstation, makes the system easy to use.

NREN: Network and Security Technology

NSA uses the Internet to provide high speed network connection among NSA, industry, and academic researchers. NSA takes the lead in developing network security and other information system security technology and products for high speed networks. It establishes high speed network testbeds to explore network and security interface technology issues.

ASTA: High Performance Systems Software, Tools, and Algorithm Research

NSA develops systems software to enhance productivity of users of high performance systems. This software includes compilers, simulators, performance monitoring tools, software that is portable among a variety of high performance systems, software for distributing jobs across a network, and visualization tools. New algorithms are developed to map problems to high performance architectures.

Time improvement using multiple processors vs. a single processor for a parallel eigensolver algorithm for large dense symmetric matrices, which occur frequently in models of physical phenomena. A parallel algorithm "scales well" when it effectively uses almost all available resources as the problem size and the number of processors increase. The achievable performance improvement is proportional to the increase in the number of processors. Parallel algorithm design and implementation is an iterative process with the goal of achieving the maximum performance possible. SRC research continues seeking ever-faster eigensolvers. These data are from the Intel Touchstone Delta at Caltech. Results are being collected for the IBM SP1, the Thinking Machines CM5, and the Intel Paragon.

IITA: Development of Dual-Use Technology

NSA proposes to investigate developmental technologies to support information infrastructure applications in manufacturing, education, public health, and digital libraries. Research and development in transaction processing, database management systems, and digital data storage and retrieval systems, are expected to make strong dual-use technology contributions to both the Federal and the IITA communities.

BRHR: Fundamental High Performance System Research and Education

NSA supports basic research into new technologies, theory and concepts of high performance computing and networking, and promotes research in high performance computing at the Institute for Defense Analyses' (IDA) Supercomputing Research center (SRC) and at universities. NSA's National Cryptologic School and the SRC develop courses suitable for users of high performance computing environments.


The overall coordination of NSA's HPCC activities resides in the office of the NSA Chief Scientist, who reports to the Director of NSA. Responsibilities for execution of major elements of the plan lie with the Technology and Systems Directorate and the Information Systems Security Directorate. NSA sponsors the SRC in exploring massively parallel computer architectures and in developing algorithms and systems software for parallel and distributed systems. The SRC heavily supports NSA's HPCC activities directly and by collaborative efforts with other HPCC participants, especially industry and academia.

FY 1994 Plans


Extend existing high performance system simulators and testbeds at NSA and the SRC.

Develop mass archival storage -- (10)15 to (10)16 bits.

Define techniques for the interoperability of distributed operating systems spanning large sets of heterogeneous computer assets, including supercomputers.

Integrate major new vector/scalar massively parallel processor as a research system.

Demonstrate a terabit/second (1012-bit-operations-per-second) deskside SIMD system.

Continue technical cooperation with major vector/massively parallel processor developers.

Investigate, cooperatively with industry, processing-in-memory (PIM) technology in established systems architectures.

Memory traffic flow from CPU memory ports through a memory arbitration network, and back to CPU input ports. Each colored rectangle represents one physical queue organized in groups. The colors represent the queue state; for example an empty queue is white and a full queue is red. The animation of this display shows memory message traffic through the memory network. Its purpose is to point out possible clogs and busy spots within the network.


Install in-house gigabit network testbed to explore high speed network architectures and techniques.

Explore network security issues for 622 Mb/s and 2.4 Gb/s networks.

Install a gigabit network testbed to explore compatibility of DOD networks with vendor-provided public networks.

Initiate development of a bulk link encryptor for high speed networks.

Develop proof of concept for cell encryption in very high speed switched network products.

Front and rear views of High Speed Network (HNET) Testbed.

These 64 Unix processors attached to 64 custom-chip switch nodes, each with seven ports, serve as a high speed network routing protocol testbed. The system can be configured to be an Asynchronous Transfer Mode (ATM) switch, for example, to allow experimentation with the efficiency of currently evolving commercial offerings.


Develop parallel extensions to high-level programming languages suitable for parallel architectures.

Develop visualization techniques for performance analysis of parallel and vector high-performance architectures.

Develop system modeling tools for heterogeneous computing environments, including high performance systems.

Develop algorithms and implementations for solving eigensystems and manipulating sparse matrices on parallel systems.

Develop evaluation testbed for exploring routing algorithms and topologies for computer interconnects.

IITA Candidates

Study applicability of heterogeneous data base technology program to information infrastructure application needs.

Investigate transferability of digital library technology to the private sector.

Research public sector security technology issues unique to the IITA as well as dual-use technologies applicable to both national security and public sector communities.


Initiate collaborative and university research efforts in performance modeling of high performance computing systems for generic problem domains.

Explore innovative parallel computer and network architectures.

Investigate new technologies in material sciences, superconductivity, optoelectronics, ultra-high-speed interconnection, and switching.

NSA has used parallel processing to greatly accelerate workstation performance. Designed and fabricated at the SRC, this board employs 32 Field Programmable Gate Arrays which are custom programmed for each application. This customization and parallelization yields speedups of 100 to 1,000 times the already impressive workstation performance. (Next section

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